As the density of semiconductor integrated circuits increases, and the corresponding size of circuit elements decreases, circuit performance may be dominated by resistive-capacitive (RC) delay, for instance, between interconnect layers. RC delay may be reduced by decreasing the overall capacitance of an integrated circuit, and its components. In particular, RC delay may advantageously be reduced by customizing interlayer dielectrics used between, for instance, adjacent metal layers of the overlying interconnect structure.
Accordingly, a need exists for reduced capacitance interlayer structures and fabrication methods.